Silicon on insulator technology (SOI) refers to the use of a layered silicon-insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics. SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or (less commonly) sapphire. The choice of insulator depends largely on intended application, with sapphire being used for radiation-sensitive applications and silicon oxide preferred for improved performance and diminished short channel effects in microelectronics devices. The precise thickness of the insulating layer and topmost silicon layer also vary widely with the intended application.
Reported benefits of SOI technology relative to conventional silicon (bulk CMOS) processing include:                Lower parasitic capacitance due to isolation from the bulk silicon, which improves power consumption at matched performance.        Resistance to latchup due to complete isolation of the n- and p-well structures.        
From a manufacturing perspective, SOI substrates are compatible with most conventional fabrication (fab) processes. In general, an SOI-based process may be implemented without special equipment or significant retooling of an existing factory. Among challenges unique to SOI are novel metrology requirements to account for the buried oxide layer and concerns about differential stress in the topmost silicon layer.
SiO2-based SOI substrates (or wafers) can be produced by several methods:                SIMOX—Separation by IMplantation of OXygen—uses an oxygen ion beam implantation process followed by high temperature annealing to create a buried SiO2 layer.        Wafer Bonding—the insulating layer is formed by directly bonding oxidized silicon with a second substrate. The majority of the second substrate is subsequently removed, the remnants forming the topmost Si layer.        Seed methods—wherein the topmost Si layer is grown directly on the insulator. Seed methods require some sort of template for homoepitaxy, which may be achieved by chemical treatment of the insulator, an appropriately oriented crystalline insulator, or vias through the insulator from the underlying substrate.        
One type of SOI wafer comprises a thin layer of single crystalline silicon extending over and insulated from the surface of a silicon substrate, and is called a “SIMOX” device. Circuits are formed in the thin layer of silicon by forming various electrical components, such as transistors, in the thin layer. One method of making a SIMOX device is to implant oxygen ions into the surface of a substrate of single crystalline silicon so that the oxygen ions are spaced from the surface of the substrate. The substrate is then heated so that the oxygen ions react with the silicon and form a thin layer of silicon dioxide beneath the surface of the substrate with a thin layer of the silicon extending over the oxide layer. See, for example, U.S. Pat. No. 5,969,923, incorporated by reference herein.
Another type of SOI wafer comprises two wafers bonded together, a first silicon substrate (or wafer) which has an oxide layer formed upon a surface thereof, which is bonded, face-to-face, with another silicon substrate (or wafer) which provides support, resulting in a silicon-oxide-silicon structure. Then, the majority of one (or the other) of the two substrates is removed, such as by backlapping, leaving a thin layer of silicon wherein circuits may be formed by forming various electrical components, such as transistors, in the thin layer. See, for example, U.S. Pat. Nos. 3,689,357 and 5,374,564.
Metallic contamination is one of the major concerns in semiconductor manufacturing. Sources of metallic contamination can include furnace anneal, chemical mechanical polishing (CMP), and wafer handling generally. Reactive and fast diffusing metal ions can cause excessive junction leakage, or even shorts, which are detrimental to the chip performance and yield. In Silicon-on-Insulator (SOI), it is particularly important to keep the metallic contamination level down, since they are easily gettered at the SOI and buried oxide (BOX) interface or BOX/substrate interface, which are very close to the active device area. A polysilicon (poly-Si) crystal layer deposited on the wafer backside has been used as a gettering layer for several years. However, the rough surface of the poly-Si layer degrades wafer flatness, which is not desirable for submicron lithography. The rough surface of the poly-Si layer may also trap or shed particles during the device processes.